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A high-throughput architecture of the CCSDS 122.0-B-1 image compression standard is proposed. The architecture uses a novel memory organization in order to reduce the total memory operations and the number of the individual memories allowing operation without external memories. The architecture has been implemented on space grade and commercial FPGA Device. It achieves 136 MSamples/sec on space grade...
Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2's complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation...
In this paper we present a parallel, FPGA-based implementation of a 256-point Fast Fourier Transform capable to perform over 78 million transformations per second. Its area of operation is located in the ultra-high speed OFDM communication in optical networks where the FFT algorithm provides the basis of the digital signal processing. The main focus lies on an implementation using as less as possible...
In recent years, China gradually put more resources in the DDS study, but it is relatively far from the international level, especially in the aspect of DDS hardware design. So, according to the status mentioned above, it was described in detail about how to simulate and achieve a DDS based FPGA in this paper. Firstly, the frame of DDS based FPGA was constructed and the algorithm was analyzed, the...
A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. The most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. The harmony between partitioning objective and timing improvement goal is kept; moreover,...
Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain design structural constraints that limit the CSS. In this paper, we present an analysis of several design structural constraints that affect the CSS and propose techniques to resolve these constraints. Furthermore, we propose a...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
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