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Upcoming mobile communication systems are more complex and comprise of sophisticated functionality to enhance their performance. To expedite their time to market, the RTL development and verification cycle time has to be improved. This paper puts an emphasis to improve the prototyping phase by using Model Based Design technique comprising of Simulink HDL coder, HDL verifier and rapid FPGA prototyping...
By applying simulation tools in many industries development centers, nowadays we see high increase in speed of technology. One of These tools is Matlab simulation environment. Getting an Automotive Transmission Algorithm from one of these Matlab Models, and being engaged in an ECU project, helped me to implement this algorithm in a new device. The main advantage of this device is having a very easy...
This paper introduced the principle of parallel prefix network (PPN) and proved the feasibility of applying PPN to differential quadrature phase-shift keying (DQPSK) precoder. Kogge Stone (KS) adder is a typical parallel algorithm of PPN. A ameliorated KS adder was proposed to implement the precoder. With 78Mb/s and 128 parallel channels, 20Gb/s DQPSK precoder was achieved in ML523 (Xilinx Virtex...
To maximize the potential of three-dimensional integrated circuit architectures, 3D CAD tools must be developed that are on-par with their 2D counterparts. In this paper, we present a statistical static timing analysis (SSTA) engine designed to deal with both the uncorrelated and correlated variations in 3D FPGAs. We consider the effects of intra-die and inter-die variation. Using the 3D physical...
This paper outlines the investigation conducted in fine tuning the performance of our automated surveillance system. The constituent components of the system must have a processing speed of less than 40 ms. This is usually considered to be a standard timing constraint for most automated surveillance systems. To meet this constraint, it is important to quantify the reduction in processing speed that...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
Field programmable gate array (FPGA) is a programmable chip that can be used to quickly implement any digital circuits. Placement is an important part of FPGA design step which determines physical arrangement of the logic blocks in the FPGA. The quality of placement of logic blocks determines overall performance of the logic implemented in the FPGA. In this paper, a number of placement optimization...
In this paper we explore microprocessor performance models implemented on FPGAs. While FPGAs can help with simulation speed, the increased implementation complexity can degrade model development time. We assess whether a simulator split into closely-coupled timing and functional partitions can address this by easing the development of timing models while retaining fine-grained parallelism. We give...
This paper introduces a methodology for using self- timed logic in FPGA-based embedded systems starting from a high-level specification of data-flow networks. It uses CodeS- imulink as an environment for code generation. The asynchronous circuits are synthesized using conventional commercial tools and we propose solutions for the issues raised. Also we describe a simple way of simulating these designs.
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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