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This paper presents FPGA based implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions i.e. Walsh function. The paper further compares Parameterized `Serial In Serial Out' architectures based on classical counter approach. The investigation consider FPGA parameters like Area, Speed and Power and shows that using Gray-increment based architecture...
This paper aims the hardware co-simulation of parameterized Walsh code with classical counter architecture using MATLAB SIMULINK based Xilinx System Generator software tools. This is an implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions such as Rademacher functions and Walsh functions. We investigate 64-orthogonal set for 3G standard such...
Single-ISA heterogeneous multi-core architecture which consists of diverse superscalar cores is increasing importance in the processor architecture. Using a proper superscalar core for characteristic in a program contributes to reduce energy consumption and improve performance. However, designing a single-ISA heterogeneous multi-core processor requires a large design and verification effort which...
In this paper, an acoustic feature extraction method based on mel frequency cepstral coefficients (MFCC) was implemented on FPGA for real-time respiratory sound analysis. The proposed technique was implemented using Xilinx System Generator (XSG) in MATLAB/SIMULINK environment. The feature vectors obtained with fixed-point XSG implementation is compared to those obtained with on the floating-point...
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating...
This survey first introduces index generation functions, which are useful for pattern matching in the communication circuit. Then, it shows various methods to realize index generation functions by using LUTs and memories. These methods are useful to design FPGAs with embedded memories.
The Merkle Signature Scheme relies on hash function and is, therefore, assumed to be resistant to attacks by quantum computers. This paper presents an efficient hardware architecture to accelerate the generation of Merkle hash trees. Timing measurements on a prototype show a considerable performance boost compared to a similar software solution.
This paper presents a sequencer that accelerates matrix algorithms arising naturally in many multimedia and signal processing applications. The accelerator has been designed to carry out data management tasks common to these algorithms. A novel event-based parameter update mechanism allows production of continuously varying patterns to access triangular, banded and other irregular matrix structures...
This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs...
This paper describes the mean square error (MSE) of basis function (BF) caused by the quantization of sine/cosine values. MSEs for all CRAIMOT BFs are equal. Additionally, MSEs are estimated for random signals synthesized by a limited number of weighted CRAIMOT BFs (partial sum). Maximal and minimal MSEs are given in dependence on the wordlength of sine/cosine former and the number of BFs used for...
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