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This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts...
This paper presents the implementation method for two signal processing structures, a digital FIR filter and a discrete Fourier transform, using programmable logic structures and VHDL hardware description language.
Parallel 1-D signal filtering algorithm is implemented as a parameterized efficient FPGA-based architecture using Xilinx System Generator. The implemented algorithm is a linear indirect filters achieved by a parallel FFT/point-by-point complex inner product/ IFFT convolution unit array. The implemented architecture manifests a 38 % higher performance per Watt at maximum frequency. The parameterized...
In this paper, we present FPGA implementation of a digital down convertor (DDC) and digital up convertor (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the circuits are verified on the Virtex-4...
In this paper, we propose the design and implementation of the digital up converter (DUC) on xilinx FPGA for WCDMA. To shorten the design cycle and increase the design productivity, a powerful system design tool, Xilinx System Generator, is adopted. Submodules of the DUC, such as the RRC filter and the half-band filters, are designed using MATLAB FDATool and Xilinx FIR Compiler. The DDS submodule...
In this paper, the design and implementation of the digital up converter (DUC) on Xilinx FPGA for WCDMA is presented. A powerful system level design tool, Xilinx system generator, is adopted to shorten the design cycle and increase the design productivity. The proposed DDC includes DDS, mixer and three cascaded stages of filters. Using Vitex-5 DSP48E slices, the maximum operation speed of the complex...
This study is a significant advancement of this team's proof-of-concept study on using field-programmable gate arrays (FPGAs) in wireless sensing for structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform. An effort is presented herein to embed algorithms to process nonlinear...
A WCDMA Digital Up Converter (DUC) design based on FPGA is presented. Aiming to shorten the design period and increase the design performance, a powerful design tool, Xilinx System Generator is used. The RRC filter and the Half-band filter are designed by using MATLAB FDATool, and implemented by using Xilinx FIR Compiler. The DDS module is generated by Xilinx DDS Compiler. Finally, the DUC design...
This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.
FFT algorithm is the popular software design for spectrum analyzer, but doesnpsilat work well for parallel hardware system due to complex calculation and huge memory requirement. Observing the key components of a spectrum analyzer are the intensities for respective frequencies, we propose a Goertzel algorithm to directly extract the intensity factors for respective frequency components in the input...
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