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This paper presents XtokaxtikoX, a fully autonomous cyber-physical system employing only stochastic arithmetic to perform computations on its data-path. Traditional implementations of stochastic computing systems benefit from fast and compact implementation of arithmetic operators, and high tolerance to errors, but depend heavily on the conversion between stochastic bitstreams and binary to implement...
An antilog is the inverse function of a logarithm. Today, conventional use of the term “antilog” has been replaced in mathematics by the term “exponent”. The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system...
Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.
This paper deals with more efficient and effective way of handling the random and busy traffic pattern on Indian roads. The purpose of this paper is to flush out the concept of nondynamic traffic light controller TLC (with fixed counters irrespective of traffic intensity) existing in INDIA and other developing nations. This AD-TLC concept will save time and will smoothen the traffic flow by avoiding...
In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable...
This paper proposes a simple but practical Gaussian-distributed pseudo-random number generator. The features of this generator include a compact architecture based on a decimator connected linear feedback shift register, Gaussian-distributed N-bit random number output, long period of a random number sequence, and good statistical properties.
This paper present a design of RSA-encryption using Pipelined radix-2 Montgomery's architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the...
Most field programmable gate array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented...
This paper reports the design of two courses, "embedded hardware'' and "embedded software" offered in 2008 spring semester at Hiroshima University. These courses use 16-bit processor TINYCPU, cross assembler TINYASM, and cross compiler TINYC. They are designed very simple and compact: The total number of lines of the source code is only 427. Thus, students can understandthe entire design...
Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a fully parallel Decimal64 floating point (FP) multiplier compliant to IEEE Std 754-2008 for floating point arithmetic. The proposed multiplier possesses novel methods to target low latency. The proposed design...
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