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One of the newest computational technologies is the high performance heterogeneous computer (HPHC) wherein dissimilar computational devices such as general purpose processors, graphics processors, field programmable gate arrays (FPGAs), etc., are used within a single platform to obtain a computational speedup. Jackson State University has a state-of-art HPHC cluster (an SRC-7), which contains traditional...
A cluster of commodity computers and general-purpose computers with accelerators such as GPGPUs are now common platforms to solve computationally intensive tasks like scientific simulations. Both technologies provide users with high performance at relatively low cost. However, the low bandwidth of interconnect compared to the computing performance hinders efficient operation of both cluster and accelerator...
A proposed UHF RFID location system, based on a known location of the reference tags by applying the cosine theorem to calculus more location information, can provide location-aware services. In this article, the trigonometric cosine and sine functions required in the computation of the law of the cosines are realized using a Coordinate Rotation Digital Computer (CORDIC) based floating-point arithmetic...
The discrete wavelet transform has taken its place at the forefront of research for the development of signal and image processing applications. Hence this paper is proposed on the work of design of hardware for the computation of Floating Point Discrete Wavelet Transform using Harr wavelet. The proposed hardware was implemented using VHDL and components were designed at the gate level. This resulted...
The paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the user defined precision. The algorithm produces...
To address the issues of single event upsets caused by radiation in outer space to micro-satellites, we proposed a novel reconfigurable on-board computer system with three soft core CPUs inside the Field Programmable Gate Array(FPGA), with the function of error detecting and restoring configuration. Two of the soft core CPUs act as the central processing unit, doing housekeeping of the satellite;...
This paper analyses structure and algorithm of floating-point ALU, and implements multiplication and division operation in the homo-hardware circuit. The floating-point multiplication and division ALU supports floating-point number according with IEEE-754 standard. This ALU adopts 4-level pipelining structure: '0' operation number check, exponent addition and subtraction operation, fraction multiplication...
In this paper we have presented an efficient FPGA implementation of a reciprocator for both IEEE single-precision and double-precision floating point numbers. The method is based on the use of look-up tables and partial block multipliers. Compared with previously reported work, the modules occupy less area with a higher performance and less latency. The designs trade off either 1 unit in last-place...
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