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In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
Abstract A new method of using Vis/NIR spectroscopy technique to identify the varieties of red wines was studied. Through comparing modeling performance built by different amounts of independent components, 20 independent components (ICs) extracted by independent components analysis (ICA) were employed as the inputs of the BP neural networks and were consider to be important parameter for calibration...
In this paper, we focus on the security issue of a chaotic digital communication scheme called chaotic-pulse- position modulation. We design a third party intrusion scheme to test to see if CPPM is as secure as is claimed. Experiments are conducted with various chaotic maps, where CPPM is used to modulate the message at the transmitter and a Kalman filter fed with a polynomial approximation is used...
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