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With supercomputer system scaling up, the performance gap between compute and storage system increases dramatically. The traditional speedup only measures the performance of compute system. In this paper, we firstly propose the speedup metric taking into account the I/O constraint. The new metric unifies the computing and I/O performance, and evaluates practical speedup of parallel application under...
Multi-core processors are commonly available now, but most traditional computer architectural simulators still use single-thread execution. In this paper we use parallel discrete event simulation (PDES) to speedup a cycle-accurate event-driven many-core processor simulator. Evaluation against the sequential version shows that the parallelized one achieves an average speedup of 10.9x (up to 13.6x)...
The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems. Furthermore, their parallelism continues to scale with Moore's law. The challenge is to develop mainstream application software that transparently scales its parallelism to leverage the increasing number of processor cores, much as 3D graphics applications transparently scale their parallelism...
The Department of Electronic Engineering of Beijing Institute of Technology is integrating emerging interconnect technologies with other high-performance technologies to meet the demanding requirement of future, real-time signal processing applications. For next-generation, scalable, modular and adaptable signal-processing system, a universal, flexible and high-performance signal processing module...
A new architecture, called isometric on-chip computer architecture (ICMA), for massive parallel computing is introduced. This architecture integrates an equal distance organization of processing elements interleaved with memory units. ICMA is inspired by the sodium chloride (NaCl) molecular structure and based on bicolor three-dimensional mesh network structure rules. In this paper, we present ICMA...
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