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In this paper, we have proposed a write efficient SRAM cell. The write power consumption is reduced compare to the 6T cell due to two extra nMOS tail transistors in the pulldown path of the respective inverter. These two tail transistors avoid the discharging of bitlines. The proposed cell is simulated with the help of the MICROWIND3 using advanced BSIM4 model. The SRAM cell is 1.85X faster and consumes...
In this paper, we present an automatic soft IP (Intellectual Property) generation method for high-speed Viterbi decoders. In our scheme, the synthesizable HDL (Hardware Description Language) code for the Viterbi decoder is automatically produced depending on not only the system parameters such as a coding rate but also the hardware architecture for parallel processing. The proposed method is implemented...
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