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In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those...
In this paper, we have proposed area-efficient 3-input decimal adders using simplified carry and sum vectors. By using proposed generator circuits and the recursive generation of correction terms, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 39.2 % area cost compared to previous reported decimal adders...
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