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Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-,...
In this paper, we have proposed a write efficient SRAM cell. The write power consumption is reduced compare to the 6T cell due to two extra nMOS tail transistors in the pulldown path of the respective inverter. These two tail transistors avoid the discharging of bitlines. The proposed cell is simulated with the help of the MICROWIND3 using advanced BSIM4 model. The SRAM cell is 1.85X faster and consumes...
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