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This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 43% improvement in power-delay product (PDP). The proposed full adder provides full-swing output with good driving capability and it is a proper choice...
This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold technology. HSPICE simulations show that the power dissipation, power delay product and square...
Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance integrated circuits often use adders to achieve...
This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
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