The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach...
In order to evaluate the actual condition of high voltage SF6 circuit breakers, a reliable measurement of their ageing and failure characteristics with suitable sensors and condition monitoring is necessary. In this paper, reliability models are developed for individual characteristic parameter such as SF6 leakage, N2 leakage, or oil leakage and control- and protection problem, etc. The physics -...
Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy and performance of a system. Since the increasing rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFM techniques are recently shown to have compromising advantages on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault...
In this paper, the effects of certain component faults on the performance of three-phase inverter-fed induction motors are analyzed under indirect field-oriented control. Simulations of faults in the current sensors, speed encoder, three-phase inverter, and motor are presented. Sample hardware faults verifying the simulation results are also presented. Performance requirements are set based on typical...
Hardware fault-insertion test (FIT) is a promising method for system reliability test and diagnosis coverage measurement. It improves the speed of releasing a quality diagnostic program before manufacturing and provides feedbacks of fault tolerance of a very complicated large system. Certain level insufficient fault tolerance can be fixed in the current system but others may require ASIC or overall...
This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach...
This paper describes modeling of power system reliability including protection failures from a new perspective. For a specific component, called focus-component, the undesired-tripping mode failure of its protection has no interaction with other components and the influence on itself can be represented by a two-state process. The fail-to-operate mode of its protection is represented by its unreadiness...
Presilicon testing and verification is a crucial step in qualifying the RTL for the subsequent implementation phases. This article presents a novel simulation-based fault injection methodology that is applied at the system description level, as opposed to the lower, flattened RT level, in order to reduce simulation time.
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.