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This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle...
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