The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Circuit camouflaging techniques have been proposed to thwart reverse engineering (RE) attacks to integrated circuits (IC). In one of the most well-known camouflaging methods, selective XOR, NAND, and NOR gates are replaced by configurable logic units which have the same appearance to the RE attackers. It is argued that a successful attack has to brute force search all the camouflaged gates' possible...
Equivalence checking and functional correction are important steps ensuring design correctness. Direct verification of large industrial designs is challenging and often requires a divide-and-conquer approach. The 2015 CAD Contest at ICCAD poses the challenge of large-scale equivalence checking and functional correction. This paper reports our work in the competition. An algorithm to identify cut-points...
In this paper, we present a heuristic algorithm for bipartitioning a netlist of modules having m types of heterogeneous resources, as in modern FPGAs with configurable logic blocks (CLBs), Block RAMs and Multipliers (MULs). The desired min-cut bipartition has to satisfy m constraints arising from given balance ratios, one for each type of resource. The netlist is represented as a hypergraph, whose...
A location-based reliable multicast algorithm for mobile ad hoc networks is proposed in this paper. A grid network with geographical location information is divided into a high-channel subnetwork and a low-channel subnetwork according to labels of grids. Then destination nodes are partitioned into groups by using location information, the multicast routing is done in label order for each group. The...
For finding the critical path in electrical circuit designs, a shortest-path search must be carried out. This paper introduces a new two-level shortest-path search algorithm specially adapted for parallelization. The proposed algorithm is based on a module-based partitioning algorithm and a shortest-path search parallelized for the usage on multi-core systems. Experimental results show the impact...
Conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over Z2n. This paper, in comparison with, presents 1) an improved partitioning heuristic based on single-variable monomials instead of checking all sub-polynomials, 2) an improved compensation heuristic which is able...
This paper presents a hypergraph partitioning based constraints decomposition procedure to guide an RTL satisfiability solver. The constraints with their correlative variables drawn from the RTL circuit are modeled as a hypergraph and techniques based on hypergraph partitioning are employed to decompose constraints. This scheme solves the partitioned problems respectively and reconciles them via cut-set...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
We demonstrate that the class of languages accepted by deterministic one-counter machines, or DOCAs (a natural subset of the context-free languages), is learnable in polynomial time. Our learning protocol is based upon Angluin's concept of a "minimally adequate teacher" who can answer membership queries about a concept and provide counterexamples to incorrect hypothesized concepts. We also...
It is shown that if a 4-by-n binary matrix has four distinct even-parity rows such that each column has exactly two 0's and two 1's, then there exists a totally self-checking even-parity checker that is tested by the four rows of this matrix. The utility of this result in designing self-testing embedded parity checkers is described.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.