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This paper presents a framework that utilizes Boolean difference theory to find test vectors for stuck-at-fault detection. The framework reads in structural-style Verilog models, and automatically injects single stuck-at-faults (either stuck-at-zero or stuck-at-one) into the models. The simulations are then performed to find minimal sets of test vectors. Using this setup, we conducted experiments...
This paper presents a c-testable motion estimation (CTME) design to efficiently detect the faults in process elements (PEs). The goal of the CTME design is to offer high reliability for video coding systems. The proposed CTME was carried out by Verilog HDL and synthesized with the TSMC 0.18 mum CMOS technology. Logic simulation results show that the proposed CTME guarantees 100% fault coverage with...
The importance of System-On-Chip (SoC) validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? An innovative domain coverage metric is proposed in this paper. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that point on or near the boundary is most sensitive to domain...
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