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ReRAM devices show potential for in memory computing systems due to their capability to both store and process data via implication logic. This type of logic, which is typically implemented using the set transition, could offer reliability and performance advantage if implemented with reset switching of the device. However, the gradual transition of the reset makes it impractical. This paper presents...
In this work, the performance and reliability analysis of a crossbar molecular switch nanomemory demultiplexer is studied and results presented. In particular, we investigate the impact on the performance of a crossbar nanomemory demultiplexer of implementing a combination of error correction coding and multi-switch junction fault tolerance schemes. Results indicate that delay and power scale linearly...
In this paper, we introduce and evaluate ScaleMesh, a scalable miniaturized dual-radio wireless mesh testbed based on IEEE 802.11b/g technology- ScaleMesh can emulate large-scale mesh networks within a miniaturized experimentation area by adaptively shrinking the transmission range of mesh nodes by means of variable signal attenuators. To this end, we derive a theoretical formula for approximating...
A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first...
Network-on-chip (NoC) architectures employing packet-based communication are being increasingly adopted in system-on-chip (SoC) designs. In addition to providing high performance, the fault-tolerance and reliability of these networks is becoming a critical issue due to several artifacts of deep sub-micron technologies. Consequently, it is important for a designer to have access to fast methods for...
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