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In this paper, the physical mechanism and models of oxide-based resistive-switching random access memory (RRAM) and the optimization of the devices and arrays are addressed and reviewed. The review focuses on our research achievements on the unified physical mechanism, physical-based models including switching and reliability behaviors, and the optimization design issues of the oxide-based RRAM.
Renewable Energy sources integration to the grid is becoming more vital due to the market share increase. The integration of PV farms, for instance, usually requires a DC-DC conversion stage to boost up the source voltage. In addition, DC-DC converters with continuous input current reduce the bulky input capacitor requirements. This saves the cost, and enhances the reliability of the system since...
The aging effect “Negative Bias Temperature Instability”, which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap...
We present a summary of results achieved in our in-field experience on Phase Change Memory characterization which directly focuses on the reliability of arrays instead of analyses of single cells. The study of large population of cells is fundamental when new failure mechanisms have to be discovered and they may occur with small probability during common writing or reading operations.
A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first...
This paper presents a performance and reliability analysis of a scaled crossbar molecular switch memory and demultiplexer. In particular, we compare our multi-switch junction fault tolerance scheme with a banking defect tolerance scheme. Results indicate that delay and power scale linearly increasing number of redundant molecular switch junctions. The multi-switch junction scheme was also shown to...
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