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In this work, a comparative study for the n-type emitter formation in the fabrication of simple structures of crystalline silicon (c-Si) solar cells is reported. Gas and spin on dopant sources were employed in the pn junction formation of the solar cells in order to compare their performance. Phosphine (PH3) was used as n-type gas for phosphorus diffusion while the Filmtronics Spin-On Dopant SOD-P905...
Inorganic nanomaterials such as nanowires (NWs) and nanotubes (NTs) are explored for future flexible electronics applications due to their attributes such as high aspect ratio, enhanced surface-to-volume ratio, prominent mobility and ability to integrate on non-conventional substrates. Device performance of semiconducting NWs are demonstrated to be superior compared to the organic counterparts. Among...
A wettability patterned surface has been developed to manipulate nucleation boiling in a micro fluid flow channel. The wettability patterns was fabricated by using hydrophobic dots on hydrophilic surfaces which form non-wetting islands and wetting network. The hydrophobic hexagon dots with a side length of 30μm and pitch distance 60μm are fabricated with Teflon (Teflon AF 400s2-100-1, DuPont) which...
Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key...
This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
Surface photovoltage (SPV) method was used to evaluate the silicon-sapphire interface potential barrier of silicon on sapphire (SOS) wafers obtained by CVD technique. The method provides monitoring of silicon-sapphire interface quality. Fabrication process parameters which influence on SPV signal were found. Silicon deposition temperature has a great importance on SPV signal. It was found that SPV...
Specifications and fabrication process suitable for a small wafer with the diameter of half-inch, which is used for a minimal fab, is presented. We beveled wafer edge by rapping and polishing in order to clean the edge and to suppress the strong surface tension at the edge. To show the crystallographic orientation of the wafer, we introduced laser marking process. By the processes, we have formed...
Through glass vias (TGVs) are a key component in glass-based interposers and microelectromechanical-system lid wafers. Magnetic-field-assisted self-assembly has been demonstrated earlier in fabrication of through silicon vias. Here we present an entirely maskless TGV fabrication process utilizing magnetic assembly. Femtosecond laser is used for ablative direct patterning of surface metal layers and...
Glass is one of the essential materials for optical devices due to its transparency. It usually loses about 4% of energy of an incident light at its interface. In order to suppress its reflection, moth-eye structure, which is the nanoscale tapered pillar array, has a remarkable anti-reflection performance. In its fabrication method, nanoimprint lithography has been paid attention due to the availability...
Here we present the fabrication process for silicon-in-glass electrodes as capacitive transducers. The embedded electrodes are formed by utilizing a glass reflow process. DRIE process easily defines the number and shape of these embedded silicon electrodes. Eight, sixteen, twenty-four electrodes are obtained through this process. These silicon-in-glass electrodes are anticipated to be operated to...
In order to remove the photoresist during the rework process, a dry rework is primarily used to ash the photoresist followed by a wet cleans process to remove the remaining organic residues. An effective process with very high particle removal efficiency (PRE) is desired at this surface cleaning step. A cleans process with lower PRE leaves particles on the wafer surface which create extra pattern...
Backside nanotexturing fabricated by electroless metal assisted wet chemical etching, protected with a deposited thin silicon layer, is a new approach to create high bending strength silicon samples. Bending strength for protected nanotextured samples followed by CMP process was enhanced by ∼3.4 folds as compared to polished silicon samples, which emphasize the possibility of industrial implementation...
This paper presents amino-terminated micro pattern transferring onto a mica substrate using polydimethylsiloxane (PDMS) soft stamp and proteoglycan (PG) molecular immobilization. PDMS bump-arrays with ultra-smooth surface were fabricated utilizing anisotropic etched silicon substrate as a mold. Coating and removal of releasing-agents were investigated to improve detachability of PDMS stamp from silicon...
Capacitive Micromachined Ultrasonic Transducers (CMUTs) are generally fabricated either by conventional sacrificial release process or by wafer bonding technique. In the former, sacrificial layers are patterned with deposited materials on the substrate. This current work reports a development on the aforementioned technique wherein sacrificial islands are embedded inside grooves opened by DRIE in...
This paper reports a single-step and cost-effective method to fabricate ultrathin Poly(dimethylsiloxane) (PDMS) membrane with honeycomb-like nanostructure on silicon substrate. The method is based on the template prepared by colloidal nanoparticles self-assembly. The thickness and nanostructure of the membrane are both determined by the size and surface morphology of two dimensional colloidal nanoparticles...
This paper reports wafer-level batch fabrication of microfluidic resonators by employing high temperature annealing of a pre-structured silicon wafer with periodic cylindrical pits for the first time. Upon high temperature annealing of pre-structured silicon, the surface silicon atoms around cylindrical pits moved and merged into long channel-shaped cavities with closed lids which are known as silicon-on-nothing...
Quantum dot structures, where electrons are confined three-dimensionally in the below 10 nm scale, show characteristics quite different from conventional bulk structures. Recent progress in the fabrication technology of silicon nanostructures has made possible observations of novel electrical and optical properties of silicon quantum dots, such as single electron tunneling, ballistic transport, visible...
In this paper we report on in-situ CCVD grown bilayer graphene transistors (BiLGFETs) in a Silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1×105 and 1×107 at room...
We have demonstrated the operation of thin body GaSb-on-insulator (GaSb-OI) p-MOSFETs on Si wafers fabricated by direct wafer boding (DWB). We have developed a wafer-scale transfer technique for transferring ultrathin GaSb layers to Si wafers. We have found that the hole mobility of the thin body GaSb-OI p-MOSFETs depends on the GaSb thickness and the GaSb channel surface condition.
This paper presents the design, fabrication, and use of silicon nanowire (SiNW) arrays-patterned microcantilever sensors excited in the in-plane resonance mode to enhance the detection of airborne particulate matter (PM). Electrothermal excitation elements of p-diffused heating resistors were introduced in the current sensor system to replace the formerly used external piezoceramic stack actuator...
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