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Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a...
VoIP is rapidly growing and widely used real-time voice service. On the path through the packet-switched networks, the regularity of VoIP stream is impaired by routing, queuing, scheduling and serialization effects, consequently resulting in loss and delay jitter of packets. Achieving high quality real-time voice requires smoothing the delay jitter at the receiver which is generally done by means...
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