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This paper presents the design of a 12 Mb/s COFDM baseband processor compatible with the standard IEEE 802.11a. In this case, the architecture was described in VHDL, without use of IP cores or automatic generators, and the COFDM baseband processor with a cyclic prefix includes coarse and fine time synchronization system, and a channel coding system composed of a convolutional encoder with interleaver...
This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. LALP is a domain specific language and its compilation framework aims to the direct mapping of algorithms originally described in a high-level language onto FPGAs. In particular, LALP focuses on loop pipelining, a key technique for the design of hardware accelerators. While...
Efficient architectures for realizing MDCT/IMDCT are presented. Based on the symmetry property of trigonometric functions, N-point MDCT formula was transferred into an odd-even index paralleling process which can be achieved by two different types of decomposition, recursive formed DCT-II kernel or FFT-based DCT-IV kernel. Then a butterfly unit is employed to accelerate the computational speed. Furthermore,...
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