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The fact that energy is a scarce resource in many embedded real-time systems creates the need for energy-aware task schedulers, which not only guarantee timing constraints but also consider energy consumption. Unfortunately, existing approaches to analyze the worst-case execution time (WCET) of a task usually cannot be directly applied to determine its worst-case energy consumption (WCEC) due to execution...
In this paper we perform an analysis of the main software methods for consumption reduction in real time systems (RTS). The study covers both scheduling methods and energy consumption models for RTS, where we focus on sensor nodes. Further on, we propose a new consumption model for a large number of node configurations, which suites most of the main scheduling algorithms. We also introduce a software...
Multi-level caches are widely used to improve the memory access speed of multiprocessor systems. Deciding on a suitable set of cache memories for an application specific embedded system's memory hierarchy is a tedious problem, particularly in the case of MPSoCs. To accurately determine the number of hits and misses for all the configurations in the design space of an MPSoC, researchers extract the...
Accelerating the time to market for new embedded real-time systems is an imperative strategy nowadays. However, releasing poor-quality designs to the market can be dangerous, since a missed deadline in hard real-time systems can be catastrophic. Thus, early detection of potential problems in these systems is mandatory, since it may reduce the risks of fault propagations from early specification to...
Energy-aware real-time (ERT) systems are increasingly complex and have pervaded various areas, from automotive to telecommunication systems. Dedicated UML-based modeling languages, such as EAST-ADL or MARTE have been proposed to harness this complexity. However, they provide limited support for modeling ERT constraints, in particular continuous energy consumption. To cope with this issue we introduce...
In this paper we use the Activity diagram of the System Modeling Language (SysML) in combination with the new UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) in order to validate functional, timing and low power requirements in early phases of the embedded system development life-cycle. However, SysML lacks a formal semantics and hence it is not possible to apply, directly,...
Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on...
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