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This paper presents a wideband low-noise amplifier (LNA) architecture that is scalable in terms of the chip area and supply voltage and therefore is expected to offer superior performance with technology scaling. In order to secure low-voltage scalability and allow for potential rail-to-rail operation under an ultralow supply voltage, the CMOS inverter is chosen as the basic amplifier stage. The core...
This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each...
In this paper, the aim of this work is to design a V-band low-noise amplifier that is suitable for SoC and wireless communication systems. It achieves a peak gain of 11.7 dB while consuming 21.6 mW.
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