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The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
This paper proposes a full custom design of a 9-write and 17-read multi-port register file. The proposed register file can fulfill one read-after-write access in one system cycle with a synchronous read and an asynchronous write. The design employs a single-ended sense amplifier and a high-speed SCL address-decoder as write decoder controlled by VCLK, which is generated through a novel positive edge...
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