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A 10-bit 3 Ms/s 90 nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode interferences. Instead of traditional voltage scaling architecture, an R-C combination based D/A converter is used to reduce the chip area. And...
A 40 MSample/s, 10-bit, 3.3V pipeline ADC is presented. In order to achieve very low power consumption, it employs a high bandwidth low-power amplifiers technique and a low power low offset dynamic comparators technique. The ADC is designed in 0.35 mum CMOS technology and occupies 1.2*0.8 mm2.
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