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A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35 mum Samsung CMOS technology, the measured...
This paper presents a new 1.2 V high power supply rejection (PSR) voltage reference. The proposed design employs a high-PSR pseudo floating voltage source and a differential-to-single-ended R-MOS capacitor signal-conditioning circuit to achieve high PSR performance metric. The high-PSR pseudo floating voltage source consists of the merged design of two Brokaw's reference circuits. The proposed bandgap...
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