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High-performance op-amps in a switched-capacitor pipelined ADC consume high power to meet accuracy and speed requirements. This is aggravated by the decrease in intrinsic transistor gain and voltage headroom in nanoscale CMOS. Developments in pipelined ADCs have taken many unique directions to address these issues. Digital calibration of nonlinearity has enabled the use of low-performance op-amps...
Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64χ inter leaved 2...
An equivalent time oscilloscope array is implemented in a 90 nm CMOS technology. A combination of adjustable termination, calibration circuitry and capacitance compensation enables driver bandwidths between 0.4 to 2 GHz for termination impedances of 20 Omega to 2 kOmega for extraction of S-parameters and delay characteristics of high impedance devices such as carbon nanotubes (CNTs) and graphene....
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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