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This paper describes the implementation of a 14-bit pipelined analog-to-digital converter (ADC) operating at a sampling frequency of 50MS/s with an effective resolution of 11.1 bit at Nyquist rate, fabricated in a 130-nm technology with a supply voltage of 1.2 volts and a power consumption of less than 110 mW. The ADC consists of differently scaled 1.5-bit pipeline stages only and dispenses with the...
This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in high-speed medium/low resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and...
Current trends in wireless communications emphasize the development of UWB (Ultra-Wide Band with bandwidths greater than 500 MHz or 20% of center frequency) radios. As the size of the digital part scales down, more and more components are being pushed into the digital domain. As a consequence of this, in receiver architectures, the ADCs are being pushed more towards the antenna in the front end. This...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC...
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