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This paper introduces the 10 b 1 MS/s 0.5 mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65 nm technology and occupies 0.111 um2. The maximum sampling rate is 1 MS/s. The simulated SNDR and SFDR are 55.6 dB and 62.7 dB, respectively at input frequency of 484 kHz. Power consumption of the data converter is...
Current trends in wireless communications emphasize the development of UWB (Ultra-Wide Band with bandwidths greater than 500 MHz or 20% of center frequency) radios. As the size of the digital part scales down, more and more components are being pushed into the digital domain. As a consequence of this, in receiver architectures, the ADCs are being pushed more towards the antenna in the front end. This...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
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