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This paper describes the implementation of a 14-bit pipelined analog-to-digital converter (ADC) operating at a sampling frequency of 50MS/s with an effective resolution of 11.1 bit at Nyquist rate, fabricated in a 130-nm technology with a supply voltage of 1.2 volts and a power consumption of less than 110 mW. The ADC consists of differently scaled 1.5-bit pipeline stages only and dispenses with the...
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
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