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Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total...
An enhanced high-efficiency switching-capacitor DC-DC voltage converter based on the combination of charge transfer switch (CTS) charge pump and cross-coupled output stage is presented. Some motivated methods to overcome the reverse charge sharing problem of traditional CTS charge pump are discussed and a new mixed structure is proposed to conquer the remaining problem of threshold drop at the output...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A novel integrated CMOS current-sensing circuit suitable for boost dc-dc converters is presented in this paper. The proposed current-sensing circuit can cancel the offset-current in the traditional current-sensing circuit, thus a higher sensing-accuracy is achieved. Moreover the op-amp used as a voltage follower is not used in the proposed current-sensing circuit. Using a standard 0.6 mum CMOS process,...
An integrated CMOS current-sensing circuit suitable for current-sensing of boost converters is presented in this paper. The simulation results verify the validity and the current-sensing accuracy of the proposed circuit. For the purpose of power saving, the supply voltage of the proposed circuit can be reduced by varying the device parameters.
This paper presents a low-voltage integrated current-mode boost converter designed with a standard TSMC 3.3/5 V 0.35-mum CMOS technology. The proposed circuit could be operated for nickel metal hydride, fuel cell and alkaline battery-powered applications. The low-voltage and high-efficiency boost converter can successfully boost IV supply to 3.3 V due to four proposed circuit structures, including...
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