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This paper demonstrates a broadband LNA for 60-GHz WPAN and a 92-GHz low-power distributed amplifier (DA) in an advanced CMOS technology. A post-processed technology (above-IC), used for packaging and bonding pads redistribution, provides ultra-low-loss on-chip passives in a cost-effective solution. In the WPAN bandwidth (57-64 GHz), the LNA has a 13.4 dB peak gain, a NF between 5.6-6.7 dB and a gain...
A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6...
A CMOS mixer was design with a new circuit scheme to realize low voltage and high linearity simultaneously. A double balanced Gilbert cell was adopted as the basic topology and TSMC 0.18 mum 1P6M CMOS process was employed for the on-chip RF circuit fabrication. The proposed new circuit scheme consists of LC-tanks as a capacitively coupled resonator for low voltage and multi-stage parallel RC networks...
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