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This paper studies application of a semi-active dual loop feedback network in an ultrawideband low-noise amplifier which has been realized in a 130-nm bulk digital CMOS process. The proposed simple feedback connection is shown to improve amplifier stability and to increase isolation, with no discernible extra cost. Measurement results support the stated benefits with stable amplifier operation in...
A switch-capacitor SDM with a controllable gain design at the signal input stage has been proposed. This gain control is realized by increasing the input sampling capacitors to obtain a higher signal gain of the first integrator. This method can greatly reduce the switch-capacitor thermal noise due to the input sampling capacitors without degrading the SDM noise shaping feature. The adaptive gain...
A 60 GHz gain block is designed in a 65 nm digital CMOS 1P9M process using only digital CMOS models and a reduced metallization stack-up height to support redistribution layer routing for flip-chip designs. The design methodology utilizes current density, distributed, and lumped modeling to predict the measured center frequency of the gain block less than 1% from the simulated values. At 1 V and 5...
A novel current-mode CMOS digitally controlled variable gain amplifier (VGA) is presented in this paper. The proposed VGA is based on new ??0.75 V digitally programmable second-generation current conveyors (DPCCII) with digital current gain control. The input stage of the DPCCII is realized using two complementary MOS differential pairs connected in parallel to ensure rail-to-rail operation. The output...
This paper deals with the problem of realizing wideband receiver front-ends in downscaled CMOS technologies, which are highly wanted for multi-standard radio receivers and cognitive radio applications. Instead of using many narrowband inductor based receivers, we prefer the use of one wideband receiver with sufficient bandwidth to cover all popular frequency bands up to 6 GHz or even 10 GHz. To relax...
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