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A set of design tools that creates the framework for a loading-edge full-custom design methodology has been developed. The tools provide the design flexibility and accuracy needed to achieve maximum performance in a quality design. Complex chips with clock rates from 90 MHz to 250 MHz have been economically built using the three latest generations of CMOS processing technologies, sized at 1.75 μm,...
In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared to an 0.8- mu m technology...
A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of...
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