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A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are...
The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns...
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