The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work presents the design of a Morse decoder implemented using fourteen different architectures described in Verilog. All designs are synthesized in FPGA and ASIC, using Xilinx ISE and Vivado for the former and Leonardo Spectrum and Design Compiler for the latter. The performance and resource requirements after synthesis of each architecture are compared to gain insight on the impact caused by...
Duty cycling has been the main concept for saving energy in sensor networks for a long time. Yet, additional overhead for synchronization and the fact that overhearing and idle listening cannot completely be prevented, motivated further research. Wake-up receiver, i.e., additional ultra-low power radios that are not switched off and can receive a so called wake-up signal, aim to fill this gap. The...
Optimizing the communication behavior of parallel applications has emerged as an important topic in parallel processing. In shared memory architectures, threads communicate implicitly through memory accesses to shared memory areas. The communication behavior can be improved by mapping threads that communicate a lot to processing units that are close to each other in the memory hierarchy, such that...
Optimizing the communication behavior of parallel applications has emerged as an important topic in parallel processing. In shared memory architectures, threads communicate implicitly through memory accesses to shared memory areas. The communication behavior can be improved by mapping threads that communicate a lot to processing units that are close to each other in the memory hierarchy, such that...
Architecture of fast data recovery was introduced into the design of the digital receiver in UHF RFID Reader. The data should be recovered in a short time for the next step of decoding. Rich synchronizing information in Miller coding was used to improve the quality of decoding in a poor situation. The architecture of fast data recovery consisted of edge detector, period measure, cnt_syn and data recovery...
To overcome the influence of Doppler shifts for the acquisition time of navigation receiver in high dynamic situation, a improved method adopts an acquisition algorithm composed of Partial Matched Filter (PMF) and Fast Fourier Transform (FFT) method. The algorithm changes the traditional two-dimensional searching strategy based on spread spectrum code phase and signal-carrier frequency into one-dimensional...
The design of spectrum monitoring receiver usually uses such a hardware model being consist of FPGA (Field Programmable Gate Arrays) and DSP (Digital Signal Processor) mainly, which requires the baseband datas and spectral datas under different bandwidths can be real-time transmitted between the FPGA and DSP. In this paper, according to the characteristics of the receiver, by using the ability, processing...
ABSTRACT The 89S52 microcontroller (MCU) is very popular among the students, teachers, engineers, scientists and amateurs to build small and cost effective projects for learning purposes and or to incorporate it in a bigger project. In these projects, the chip remains in the system and occasionally need arises to change the program bytes of the code memory (flash) without removing the MCU from the...
In this paper, we propose a symmetric encryption algorithm for RFID systems called RBS (Redundant Bit Security). RBS is based on inserting redundant bits into the original data bits. The location of redundant bits inside the transmitted data represents the secret key. The redundant bits are generated by Light Weight Mac algorithm in order to provide integrity and authentication as well. The implemented...
Orthogonal Frequency-Division Multiplexing (OFDM) systems can efficiently combat the issue of frequency-selective fading channels. Therefore, OFDM has become one of the most popular baseband modulation techniques for wireless communications. This paper presents the design and implementation of a low-power OFDM baseband receiver for wireless local area networks (WLAN). The proposed architecture employs...
In order to solve the data security, reliability problems of wireless communication in the ETC embedded data-communication system, this paper has analyzed the hardware structure which the system required, and paid an in-depth study on AES encryption algorithm that the hardware encryption engine applied. On this basis, the article has proposed the proposal that taking advantage of AES hardware encryption...
TCP/IP offload engine (TOE) is an essential technology to increase throughput of network connection. In this paper we present a novel approach for TOE implementation in embedded system with very stringent requirements on area and power. Our approach is based on two design optimizations. The first one deals with architectural enhancement for reducing the size of memory buffers in TOE hardware. The...
Covert channel attacks pose a threat to the security of critical infrastructure and key resources (CIKR). To design defenses and countermeasures against this threat, we must understand all classes of covert channel attacks along with their properties. Network-based covert channels have been studied in great detail in previous work, although several other classes of covert channels (hardware-based...
This paper studied about micro controllers interaction using RS232 as a communication tool and C to programming the interaction. PIC18F4520 will be used in this prototype and MPLAB as a software tool. Before run it into the real hardware, some simulation must be done to make sure all the hardware connection and software writing is correct. Proteus 7.1 has been used for the simulation purpose. The...
Last year we were able to break KeeLoq, which is a 64 bit block cipher that is popular for remote keyless entry (RKE) systems. KeeLoq RKEs are widely used for access control purposes such as garage openers or car door systems. Even though the attack seems almost straightforward in hindsight, there where many practical and theoretical problems to overcome. In this talk I want to describe the evolution...
A concept of an asynchronous analog-to-digital converter (AADC) with on-chip hardware I2C-bus interface is presented in the paper. To our knowledge, this is the first concept enabling the operation of the AADC in the I2C communication system. Since the AADCs produce output data irregularly in time, the converter interface is equipped with the ability to initiate the transmission on the I2C bus as...
Pharmaceutical medication devices are used to fill, count, package & deliver medicines ensuring an automated & efficient batch production. Different types of devices are used but the theme here is to increase the efficiency by introducing supervisory control and data acquisition system (SCADA) which overcomes human intervention and increases the overall efficiency of the pharmaceutical process...
A hardware design of receiver which uses the FPGA + DSP + ARM structure is presented in this paper. The communication between functional units and display control units are discussed on the research of integrated OEM board for traditional receivers. The experiment result shows that the signal platform has the low power dissipation, small size, high performances, so it is very suitable for radio receiving.
In order to increase transfer rate and enhance performance in mass data transmission and storage in real time system, a high performance Serial Advanced Technology Attachment generation 2(SATA II) host controller is proposed in this paper. This paper presents how to improve the hardware performance in course of implementation and validation. The controller was designed using VHDL and developed in...
As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.