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This paper presents the implementation of curve on FPGA circuit (Field Programmable Gate Array) Spartan 3 of Xilinx, it based on Taylor approximation by segment, used third order polynomial in order to reduce the maximum error. First of all, we have stocked all coefficients, computing with Mat lab tool, in the block memory. After that, an architecture is proposed and implemented under ISE9.2i environment...
3D surface measurements have many industrial and medical applications. We have previously used 3D surface deformation and tracking to identify mechanical properties of the skin. To be able to detect dynamic changes in the surface of the skin we need to have a real-time 3D measurement system. A significant portion of the computation time for tracking the changes is spent during 2D cross-correlation...
The paper describes a Field Programmable Gate Array (FPGA)-based lossless data compression coprocessor using implementing a compression method developed by Rice. We have implemented the Rice code (both encoder and decoder) for 8 bit/sample data on an FPGA Xilinx XC4005. The code has been designed to be optimal on 1.5 < H < 7.5 bits/sample, that is usually required in lossless image...
Power electronic converters used in distributed power generation systems need grid synchronization systems. These synchronization methods can be divided into two fundamental parts. Whereas the first part proposes detecting grid signal sequences and harmonics, the second one is based on a PLL (Phase Locked Loop). DSC (Delay Signal Cancellation) y DSOGI-QSG (Dual Second Order Generalized Integrator-Quadrature...
In this paper a FPGA implementation of a cellular automaton defined by rule 101 and it's negate is presented. Such HCA (hybrid cellular automata) was previously proved to behave as a pseudo noise sequence generator with the additional binary synchronization property and with demonstrated capabilities in reducing the overall complexity of image transmission systems. The raster scan is replaced by a...
Modern codes such as Turbo and LDPC codes operate at low signal-to-noise ratios, which makes carrier synchronization a challenging problem. Hence in many waveforms, some known symbols are inserted periodically into the data stream to achieve Data-Aided (DA) synchronization. However, these known symbols decrease the throughput of the transmissions. The data symbols which are unknown can also be used...
In this paper, we propose a hardware implementation of a Feed-Back Chaotic Synchronization (FCS) for designing a real-time secure symmetric encryption scheme. This proposed scheme allows for the design and implementation of real time synchronization between two embedded chaotic generators for secure communications. The implementation and experimental results mapped on two Xilinx FPGA Virtex technology...
This paper describes a Field Programmable Gate Array (FPGA) implementation of a Digital Front End (DFE) block for a Multi-Carrier Multi-Antenna (MCMA) system. The decimation/ interpolation filters used for obtaining the required channel bandwidth are split into several low order decimation/ interpolation stages, each of them being implemented as a polyphase filter. At the receiver, the DFE contains...
Carrier Frequency Offset (CFO) estimation and correction is a critical issue in all OFDM receivers. For WiMAX Physical layer it is even more challenging to introduce a suitable CFO sub-system since WiMAX system supports complex features for future applications such as multiuser, multi-access and high mobility operation. This paper is concerned with low cost hardware implementation of CFO sub-system...
This paper proposes a high-resolution Digital-PWM (DPWM) architecture for high-frequency low-power Switching Mode Power Supply (SMPS). The proposed DPWM takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA, and combines a counter-comparator with a Multi-stAge-noise-SHaping (MASH) Delta-Sigma (Delta-Sigma) modulator. An 11-bit effective prototype DPWM along with...
This paper presents a FPGA implementation of an OFDMA modem for the physical layer of LTE technology, suitable for both uplink and downlink transmission. The designed structure achieves a low area occupation while fulfilling LTE requirements.
In this paper useful methods of concurrent processes synchronization in UML state machine diagrams are presented. It is not easy to transform complex behaviour description into statecharts, even if the formal specification has already been given, for example as a hierarchical Petri net. Both graphical forms of specifications can be used simultaneously, especially when overlapped concurrent processes...
Spread spectrum technology can effectively solve the problems such as bad channel environment, multi-path fading etc between mobile station and subscribers. At present the research on the synchronization of PN code is more concentrated on how to implement fast acquisition. This paper introduces the sliding correlation method of PN code acquisition, gives out a serial and parallel acquisition method...
Due to aggressive technology scaling VLSI circuits have become more susceptible to transient errors. The associated reduction in supply voltages has decreased noise margins, causing system reliability to be reduced increasingly at a time when electronic systems are being used in ldquosafety criticalrdquo applications. Clock distribution issues as well as the demands for low power circuits have exposed...
This paper proposes a novel preamble structure and a timing synchronization method for OFDM systems. The preamble structure has both properties of delayed and symmetric correlations which can afford accurate time and frequency synchronization simultaneously. A new timing metric is also proposed according to the preamble structure, which is the production of the modulus of delayed and symmetric correlation...
This paper proposes an improved scheme of a spread spectrum transceiver based on FPGA, which is capable of meeting wide application requirements. In order to improve the efficiency, two critical modules are refined, one is a modified matched filter, and the other one is an improved digital carrier recovery loop. Compared with the typical matched filter scheme, the modified one can save about 31.48%...
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