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Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR...
This paper describes a reconfigurable hardware implementation for wideband fractional delay FIR filters. The proposed implementation is based on a multirate Farrow structure, reducing in this way the arithmetic complexity compared to the modified Farrow structure, and allowing on line fractional delay value update. A minimax frequency optimization technique is used for computing the structure coefficients...
This paper describes a synthesis design from the MATLAB model into VHDL of a digital interpolation filter algorithm, used in a ΔΣ digital-to-analog converter (DAC), intended for Professional digital audio system. The whole filter system simulation, VHDL implementation and field programmable gate array (FPGA) verification are processing. The register transfer level (RTL) simulation result show an achieving...
Real-time wireless channel simulators are necessary for radio prototyping. Doppler filter is one of the basic building blocks in correlation-based channel simulators. Enormous computational complexity of channel models for new wireless standards like MIMOs prohibit their software realizations (which have traditionally been the case). In first part of this work, we dimension and compare two alternative...
A transmultiplexer mathematical model is presented to show the principle features of algorithm used to design transmultiplexers. Solutions of a set of the bilinear algebraic equations constitute coefficients for FIR filters to achieve the perfect reconstruction of transmitted signals. Simple method to solve this set of equations and to design transmultiplexer systems equipped with integer-to-integer...
The inherent reconfigurability of FPGAs enables us to optimize an FPGA implementation in different time intervals by generating new optimized FPGA configurations and reconfiguring the FPGA at the interval boundaries. With conventional methods, generating a configuration at run-time requires an unacceptable amount of resources. In this paper, we describe a tool flow that can automatically map a large...
In this paper, field-programmable gate array (FPGA) implementations of FIR Nyquist filters are presented. Array processor realizations for FIR Nyquist filter are considered and analyzed, namely the direct, transposed, hybrid, and folded forms. Design examples are considered for low-delay and linear-phase FIR Nyquist filters. The filters are then realized as a combination of the appropriate structures...
This paper presents the design and FPGA implementation for different order pulse shaping finite impulse response (FIR) filters. In this paper, the coefficients of the implemented filters have been modified with an optimization algorithm proposed in an earlier work. The use of this algorithm results in reducing the number of non-zero coefficients used to represent the filter's frequency response. Reducing...
A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware...
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