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In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3bit...
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented...
Carrier Frequency Offset (CFO) estimation and correction is a critical issue in all OFDM receivers. For WiMAX Physical layer it is even more challenging to introduce a suitable CFO sub-system since WiMAX system supports complex features for future applications such as multiuser, multi-access and high mobility operation. This paper is concerned with low cost hardware implementation of CFO sub-system...
Multistage parallel interference cancellation (MPIC) based detectors allow to mitigate multiple access interference and intersymbol interference in direct-sequence code division multiple access (DS-CDMA) systems. Better performance is obtained when decision feedback (DF) is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared...
Wideband code division multiple access (WCDMA) technology has emerged as the most widely adopted air interface technology for the third generation universal mobile telecommunication system (UMTS) network architecture. This paper presents an FPGA implementation of a WCDMA system on a Xilinx XC3S500E-5FG320 FPGA chip. A comparison between the bit error rate (BER) performance of the proposed FPGA architecture...
Spread spectrum technology can effectively solve the problems such as bad channel environment, multi-path fading etc between mobile station and subscribers. With the rapidly development of micro-electronic and EDA technology, now the research on base band signal treatment is more concentrated on how to implement high system performance and low bit error rate. This paper introduces a new error correction...
Multiple Input Multiple Output (MIMO) system is a key technology for future high speed wireless communication standards like 802.11n, WIGWAM, and WiMax. These standards require support for multiple modulation and coding schemes. Hence, the receiver hardware should be able to accomodate these schemes preferably on a single reconfigurable architecture. Current MIMO detector implementations are constrained...
This paper presents an FPGA implementation of the vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock...
In this paper, we study FPGA implementation of a novel receiver diversity combining technique, RMSGC for wireless transmission over fading channels in SIMO systems. Prior published results using ML-detected RMSGC diversity signal driven by BPSK showed superior bit error rate performance to classical diversity combining schemes. RMSGC was shown to be near-optimal in the sense that it was very close...
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