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Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR...
In wireless communication, equalization is an effective technology to change channel characteristics and reduce the Inter-Symbol Interference (ISI). Based on analyzing the LMS algorithm, the application of this algorithm in channel equalizer is studied. A Channel Equalizer based on LMS algorithm is implemented using Xilinx System Generator for DSP develop software. This implementation method is a...
The paper discusses the design and implementation of LMS filter in the MEMS gyro control system in order to improve the precision. The design is established and then simulated using DSP Builder. And the FPGA-based system structure of LMS algorithm is synthesized and simulated on Quartus II platform and Cyclone II family, and the simulation results show that it is reliable and high precision.
Many DSP applications require a complex sinusoid to accomplish various signal rotation tasks. Examples include the discrete, fast Fourier transforms and digital up/down conversions. This article presents a complex oscillator based on the unfolded CORDIC algorithm and produces periodic sine and cosine samples for any specified angle increment. Low phase noise is achieved by residual angle correction...
Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and digital signal processors. Several compression/decompression schemes were developed and well estabilished. Most of them adopt the modified discrete cosine transform (MDCT) and its inverse version (IMDCT). In this paper we present a FPGA implementation of a fast rotation-based...
Based on the newly proposed cyclic shift orthogonal keying (CSOK) scheme, this paper presents the top-down design and realization of a dual-mode single-carrier/multi-carrier (SC/MC) spread spectrum (SS) system, including a new DQPSK-HCSOK hybrid modulation scheme and associated differential receiver. Packet and preamble formats are also designed for packet detection, CFO compensation, and channel...
In this paper, the details of implementation of an isolated digit recognition system using NiosII soft-core processor are presented. Mel Frequency Cepstral Coefficients (MFCC) is used for feature extraction, multi layer perceptron (MLP) is used for classification and self organized feature map (SOFM) is employed for dimensionality reduction of features. Using TIDIGITS speech data base, various MLP...
The application of independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the limited size and of the microelectronics technology of the used hardware devices, many practical problem can be encountered to reach the real time processing since the application of the...
A phase locked loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable gate array (FPGA) technology is used to implement a prototype. The random sampling scheme is used to reduce the sampling frequency requirements without aliasing effects. The possibility of sampling and processing at lower frequencies allows the implementation of complete-digital...
Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and DSPs. Several compression schemes were developed. Most of them adopt the MDCT/IMDCT. This paper presents a FPGA implementation of a fast MDCT algorithm. An investigation of different approaches of implementation and usage of standard embedded FPGA elements for specific...
This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (sum of absolute differences) computation. To reduce its computational complexity, SADs are computed using images divided into nonoverlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture...
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