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The feature-extraction algorithm, developed for the digital front-end electronics of the electromagnetic calorimeter of the PANDA detector at the future FAIR facility, is implemented in VHDL for a commercial 16 bit 100 MHz sampling ADC. The use of modified firmware with the running on-line data-processing algorithm will allow to perform realistic performance studies of the calorimeter and test a trigger-less...
A high resolution time to digital conversion (TDC) module has been developed for the readout of drift tubes in the PANDA detector system planned at the future FAIR facility in Darmstadt, Germany. The board is designed as a double width compact size MicroTCA module. The backplane communication is based on PCI Express according to AMC.1. PCI Express is implemented with a Xilinx XC5VLX30T FPGA using...
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