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This paper presents a program, the implementation of 1024-Point FFT algorithm based on FPGA. Considering from the operation speed and implementation complexity, this design adopts the algorithm of radix-2 and decimation in time. And cure the data of twiddle factor in the ROM block. This design uses the finite state machine control reading the data of twiddle factor, as well as coordinate each modules...
The computation amount of SAR radar image is huge. To reach real-time speed, we need high-function device. The computation task of SAR concentrates on range and azimuth compressions. Usual measure of compression is using high speed DSP, but FPGA technique is improving so fast that it has become a better way to realize compression than DSP. DSP often needs external interface and control chips to work...
This paper designs and realizes a synthetic aperture radar (SAR) real-time processor by FPGA chip, Radix-4FFT is the kernel processing in compression algorithm of SAR; The memory organization of Radix-4 FFT is considered. The design of the block floating Radix-4 FFT is valuable in military and civil application, and the complete of transpose is valuable for the later SAR real-time processing research...
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