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A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a...
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical...
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory...
The 10-b, 10 MHz BiCMOS A/D (analog-to-digital) converter with a triple-stage conversion scheme, combined with two novel conversion schemes, the dynamic sliding reference method and the triangular interpolation method, has been developed. This novel conversion scheme and BiCMOS circuit technology reduce element counts of bipolar transistors to only 2000. A small active area of 2.5×2.7 mm...
A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time...
A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero...
SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance...
A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied...
The n-channel MOSFET transient substrate current during dynamic hot-carrier stressing has been found to be a strong function of the rise and fall time of the gate/drain voltages. At fast rise and fall times (<10 ns), the displacement current associated with the dynamic stressing becomes a significant portion of the transient substrate current. The magnitude and direction of displacement current...
It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly...
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