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A CBi-CMOS IC, with complementary high-performance bipolar and CMOS on the same wafer, is reported. The structure is based on a self-aligned high-speed bipolar process called super self-aligned process technology or SST. The fabrication process is described, and its feasibility is confirmed by evaluating some devices fabricated by this technology. With a single 5-V supply, a propagation time delay...
The presence of active bipolar transistors in a BiCMOS technology increases the latchup susceptibility compared to pure CMOS processes, due to the injection of carriers in the substrate when the device is switched into saturation. The firing of the parasitic thyristor due to transient forward signals on a diode and the influence of the active bipolar transistors on this firing are examined. It is...
SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance...
A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied...
Submicrometer CMOS devices were integrated with self-aligned double-polysilicon bipolar devices, showing a cutoff frequency of 16 GHz and an ECL circuit speed of 65 ps/gate. It was found that an amorphous silicon film deposited at 575 degrees C and used as the base electrode improve the gate oxide breakdown voltage compared to a polysilicon film deposited at 600 degrees C. The PMOS FETs showed good...
High-voltage complementary pullup and pulldown devices have been fabricated in a high-voltage integrated circuit process that is based on thin epitaxial layers (<10 mu m). The device structures described allow high-voltage pullup devices to be realized where normally only pulldown devices would be possible in such thin epitaxial layers. Only one additional mask was needed to incorporate these devices...
The authors describe a submicron BiMOS process in which the lateral BJTs (bipolar junction transistors) are so similar to the MOSFETs that no extra process steps are needed. A lateral npn BJT with beta higher than 1000 has been demonstrated. A lateral pnp BJT with high cutoff frequency has been demonstrated, provided the parasitic capacitances are minimized. It is believed that this lateral BJT can...
The optimization of a submicron BiCMOS well design is described. The use of buried layers, a thin intrinsic epi layer, and a double n-well implant creates steeply graded well profiles which result in improved circuit performance due to lower diode capacitance. High contact resistance to the buried n+ layer is avoided by using a novel polysilicon plug contact process which also eliminates lateral n+...
A power integrated circuit technology capable of integrating complementary power double-diffused MOS (DMOS) output devices with high-performance BiCMOS analog and digital components is described. The PDMOS output device is incorporated to address the class of applications which require complementary power outputs, but for which lateral p-n-p bipolars or charge-pumped NDMOS transistors are unsuitable...
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