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A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical...
A 16×8 nonblocking crosspoint switch with ECL (emitter-coupled logic)-compatible input/output buffers using full CMOS technology is described. For high-speed operation above 150 Mb/s, the authors designed two ECL-CMOS translator cells for the external interfaces. One is an input buffer cell with ECL-to-CMOS level conversion, and the other is an output cell with CMOS-to-ECL level conversion...
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