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A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%....
SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance...
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