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A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of the cell horizontal access transistor in bulk material epitaxially grown over the trench capacitor. The via connection between the access transistor...
The authors propose HEMT (high electron mobility transistor) VLSI technology using nonalloyed ohmic contacts. For large integration levels, nonalloyed ohmic contacts have two advantages. One is their extremely short ohmic length, and the other is that direct connection between source/drain and gate can be made with the same metal. The propagation delay time of a ring oscillator with one-metal simultaneous...
A second-generation three-dimensional stacked capacitor cell has been developed. This cell has two significant features. One is that the three-dimensional feature of the storage capacitor has been considerably enhanced by means of a fine structure. The other is that bit lines have been formed before storage capacitor formation. Either of these features will lead to the realization of 16 M DRAMs (dynamic...
SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance...
A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied...
A novel process sequence fabricating stacked capacitor cells has been developed for high-density dynamic RAMs (random access memories). Enhanced cell capacitance can be obtained by opening the contact window for the lower electrode of the stacked capacitor after the deposition of the electrode poly-Si. This is followed by additional substrate Si etching. The procedure results in sufficient cell capacitance...
The n-channel MOSFET transient substrate current during dynamic hot-carrier stressing has been found to be a strong function of the rise and fall time of the gate/drain voltages. At fast rise and fall times (<10 ns), the displacement current associated with the dynamic stressing becomes a significant portion of the transient substrate current. The magnitude and direction of displacement current...
The authors describe key points of 0.5- mu m technologies for fabricating high-density memory devices such as 16-Mb DRAM (dynamic random access memory). The main features of the technologies are the use of field-shield isolation and a W contact source/drain transistor utilizing silane reduction of WF/sub 6/. The field-shield isolation technology enables the isolation region to be reduced down to half...
A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and polarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width...
The effects of n-well doping profile on the characteristics of SPT DRAM (substrate plate trench dynamic random access memory) data retention time are described and characterized. A retrograde n-well is shown to be desirable since it offers decreased well resistance without the modification of surface device characteristics. Retention time can be further improved with an n-well doping concentration...
Numerical simulations for the response of inverters to high-energy ion strikes are used to compare the single-event-upset (SEU) hardness of p- versus n-well technologies. A constant-geometry, mirror-image technique is used to generate the technology designs, with the objective of presenting features inherent to the well type. The p-well exhibits better SEU tolerance at low ion energies, but in the...
The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an...
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