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The advancement of bipolar VLSI technology coupled with the lower complexity of RISC (reduced instruction set computer) architectures has made possible bipolar ECL (emitter coupled logic) implementations of single-chip instruction units with much higher clock rates. It is projected that future RISC generations will be implemented in BICMOS as well as ECL and CMOS. It is concluded that ECL-based technology...
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a...
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical...
A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large <e1>I</e1>SR and small reverse mode current gain are required for the fast write operation
It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly...
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