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This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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