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A single-ended wideband low noise amplifier (LNA) for GSM (DCS1800, PCS1900) and WCDMA (Band I to IV) were designed and implemented using 0.18 mum CMOS technology. The circuit topology is based on inductively-degenerated common-source (IDCS) using on-chip inductors at the input circuit for input matching and shunt-peaking components for bandwidth enhancement at load tank. Post layout simulation results...
In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the divider's performance. The...
In this paper, a 10-Gb/s limiting amplifier (LA) was implemented in 0.18 mum CMOS. Modified active inductors and active feedback topology are employed to eliminate the trade-off among circuit bandwidth, power dissipation, and layout area, which is suitable for low cost applications. Based on the measurement results, the realized LA can operate up to 12-Gb/s with a 125 mVpp single-ended output through...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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